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1) READA ≥ t RAS (min) - (BL/2) x t CK
Internal precharge operation begins after BL/2 cycle from Read with Auto-precharge command.
2) t RCD(min) ≤ READA < t RAS(min) - (BL/2) x t CK
Data can be read with shortest latency, but the internal Precharge operation does not begin until
after t RAS (min) has completed.
This command must not be interrupted by any other command.
8.2.8
Mode Register Set Command
( RAS = “L”, CAS = “L”, WE = “L”, BA0 = “L”, BA1 = “L”, A0 to A1 1 = Register Data)
The Mode Register Set command programs the values of CAS Latency, Addressing Mode, Burst
Length and DLL reset in the Mode Register. The default values in the Mode Register after power-
up are undefined, therefore this command must be issued during the power-up sequence. Also,
this command can be issued while all banks are in the idle state. Refer to the table for specific
codes.
8.2.9
Extended Mode Register Set Command
( RAS = “L”, CAS = “L”, WE = “L”, BA0 = “H”, BA1 = “L”, A0 to A1 1 = Register data)
The Extended Mode Register Set command can be implemented as needed for function
extensions to the standard (SDR-SDRAM). Currently the only available mode in EMRS is DLL
enable/disable, decoded by A0. The default value of the extended mode register is not defined;
therefore this command must be issued during the power-up sequence for enabling DLL. Refer to
the table for specific codes.
8.2.10 No-Operation Command
( RAS = “H”, CAS = “H”, WE = “H”)
The No-Operation command simply performs no operation (same command as Device Deselect).
8.2.11 Burst Read Stop Command
( RAS = “H”, CAS = “H”, WE = “L”)
The Burst stop command is used to stop the burst operation. This command is only valid during a
Burst Read operation.
8.2.12 Device Deselect Command
( CS = “H”)
The Device Deselect command disables the command decoder so that the RAS , CAS ,
WE and Address inputs are ignored. This command is similar to the No-Operation command.
8.2.13 Auto Refresh Command
( RAS = “L”, CAS = “L”, WE = “H”, CKE = “ H ”, BA0, BA1, A0 to A1 1 = Don’t Care)
AUTO REFRESH is used during normal operation of the DDR SDRAM and is analogous to CAS –
BEFORE – RAS (CBR) refresh in previous DRAM types. This command is non persistent, so it
must be issued each time a refresh is required.
The refresh addressing is generated by the internal refresh controller. This makes the address
bits “Don’t Care” during an AUTO REFRESH command. The DDR SDRAM requires AUTO
REFRESH cycles at an average periodic interval of t REFI (maximum).
Publication Release Date: Jan. 14, 2014
- 11 -
Revision: A04
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